Learning Verilog for FPGA Development

Course details

FPGA development requires a big switch from more typical programming processes. In order to get an FPGA-based embedded system up and running, developers must add a hardware description language to their repertoire. In this course, Eduardo Corpeño helps you learn the fundamentals of one such language: the popular and concise Verilog. Eduardo begins with the basics; he explains what a hardware description language is and some similarities to traditional programming languages. He then covers the basic syntax of Verilog, as well as how to create test bench modules to run simulations, use variables with operators as an advantage of the behavioral level of abstraction, and more. Along the way, he provides demos and programming challenges that allow you to put your new skills to the test.

Topics include:
- The purpose of hardware description languages
- The different abstraction levels of a digital system
- The structure and syntax of a module in Verilog
- The uses of range specification
- If-else statements
- Boolean expressions
- The nature and limitations of simulations
- Combinational and sequential systems

Concepts

0. Introduction

01 - Verilog - Your key to digital design
02 - What you should know
03 - Setting up your environment

1. Hardware Description

04 - Hardware description languages
05 - Digital systems
06 - Levels of abstraction
07 - Gate level
08 - Register-transfer level

2. Basic Verilog Syntax

09 - Verilog modules
10 - Instantiating modules
11 - Gates and primitives
12 - Registers and wires
13 - Range specification
14 - Numbers and constants
15 - Always blocks
16 - The if-else statement
17 - Case statements
18 - Boolean algebra expressions
19 - Continuous assignments
20 - Blocking assignments
21 - Nonblocking assignments
22 - Challenge - From schematic to code
23 - Solution - From schematic to code

3. Simulation

24 - Simulation basics
25 - Test bench modules
26 - Stimulus variables
27 - Clock generation
28 - Initial and always blocks
29 - A simple simulation
30 - Timing directives
31 - Display tasks
32 - Challenge - You run the show
33 - Solution - You run the show

4. Combinational Systems

34 - Arithmetic and logic operators
35 - Challenge - Make a 4-bit arithmetic logic unit (ALU)
36 - Solution - Make a 4-bit arithmetic logic unit (ALU)
37 - Getting your ALU on a field-programmable gate array (FPGA)
38 - A functional demo of the ALU

5. Sequential Systems

39 - Flip-flops
40 - Edge sensitivity
41 - A shift register example
42 - Challenge - Make a clock divider
43 - Solution - Make a clock divider
44 - Getting your clock divider on an FPGA
45 - A functional demo of the clock divider

Conclusion

46 - Next steps

Learning Verilog for FPGA Development

Authors

Eduardo Corpeño